#ifndef CPU_INFO_H
#define CPU_INFO_H

namespace fw
{
	class CPUInfo
	{
	public:
#define cpuid(info, x) __cpuidex(info, x, 0)

		struct CPUExtensionsSupport
		{
			bool HW_MMX;
			bool HW_x64;
			bool HW_ABM; // Advanced Bit Manipulation
			bool HW_RDRAND;

			//  SIMD: 128-bit
			bool HW_SSE;
			bool HW_SSE2;
			bool HW_SSE3;
			bool HW_SSSE3;
			bool HW_SSE41;
			bool HW_SSE42;
			bool HW_SSE4a;
			bool HW_AES;
			bool HW_SHA;

			//  SIMD: 256-bit
			bool HW_AVX;
			bool HW_XOP;
			bool HW_FMA3;
			bool HW_FMA4;
			bool HW_AVX2;
		};

		CPUInfo();
		virtual ~CPUInfo();

		bool Initialize();

		void ParseExtensionsSupport();

		uint16 GetLogicalProcessorCount();
		uint16 GetPhysicalProcessorCount();

		uint16 GetSystemProcessorCount();

		uint16 GetL1CacheCount();
		uint16 GetL2CacheCount();
		uint16 GetL3CacheCount();

		DWORD GetL1CacheSize();
		DWORD GetL2CacheSize();
		DWORD GetL3CacheSize();

		const CPUExtensionsSupport& GetExtensionsSupport();

	private:
		void ParseSystemProcessorCount();
		bool ParseProcessorData();
		uint32 CountBits(uint64 bitMask);

	private:
		uint16 m_iPhysicalProcessorCount;
		uint16 m_iLogicalProcessorCount;
		uint16 m_iProcessorCoreCount;

		uint16 m_iProcessorL1CacheCount;
		uint16 m_iProcessorL2CacheCount;
		uint16 m_iProcessorL3CacheCount;

		DWORD m_iProcessorL1CacheSize;
		DWORD m_iProcessorL2CacheSize;
		DWORD m_iProcessorL3CacheSize;

		CPUExtensionsSupport m_extensions;
	};
}

#endif